1. Field of the Invention
The present invention relates generally to processors, and in particular to methods and mechanisms for handling microcode instructions in a processor pipeline.
2. Description of the Related Art
Microcode instructions are used by some processors to perform specialized routines. The term “microcode” may be defined as hardware-level instructions and/or data structures involved in the implementation of higher level operations. A microcode instruction may also be defined as a complex instruction. Microcode may also refer to instructions in an instruction set architecture that are not directly executable by an execution unit of the processor and therefore may require additional translation before being executed. Microcode instructions may be translated, or “cracked”, into a sequence of circuit-level operations that are stored in a memory (e.g., read-only memory (ROM)), via one or more table look-up operations. The cracked operations may be referred to variously as “micro-operations”, “micro-ops”, or “uops”.
In a standard operation, a processor detects a microcode instruction in the pipeline, the microcode instruction is cracked into a sequence of micro-ops suitable for execution by an execution unit, and then the micro-ops are dispatched to the next stage in the pipeline. Generally speaking, a processor pipeline comprises a plurality of pipeline stages in which various portions of processing are performed. Typically, the entry and exit points for cracking microcode instructions introduce “bubbles” (i.e., cycles when no productive operations are being performed) into the pipeline. These bubbles may delay the execution of subsequent instructions and negatively impact overall processor performance. The bubbles may also prevent the processor from maintaining a maximum instruction throughput rate.